In a semiconductor memory module, such as an FBDIMM (Fully Buffered Dual-In line Memory Module), for example, a plurality of semiconductor memory components which are driven by a memory controller via a control component, for example a hub chip, rather than directly, are arranged on a module board. Four FBDIMM module cards which differ in terms of their clock frequency and their bit rate, inter alia, have been standardized at the present time. The FBDIMM cards that have been standardized at the present time include the FBD400 card having a bit rate of 400 Mbit/s, the FBD533 card having a bit rate of 533 Mbit/s, the FBD667 card having a bit rate of 667 Mbit/s and the FBD800 card having a bit rate of 800 Mbit/s.
In a 2R×4 design configuration, 18 memory chips are situated per “Rank” on a DIMM module. The memory chips are arranged in the semiconductor memory components on the module board in a stacked arrangement (Stacked DRAM Device). In a 2× stack (Dual Stack) design, two memory chips are arranged in stacked manner within a semiconductor memory component. The individual memory chips are driven by a control circuit on the hub chip for storing or for reading out a stored information item via control, address, and clock buses. In an FBDIMM memory module of the 2R×4 configuration, the control circuit of the hub chip makes four clock signals available, of which two clock signals are used for supplying the memory chips arranged on a left-hand side of the hub chip, and two clock signals are used for driving memory chips arranged on a right-hand side of the hub chip. Given a total of 36 memory chips present on an FBDIMM module of the 2R×4 configuration, nine semiconductor memory components each having two memory chips are arranged on the left-hand side of the hub chip and nine semiconductor memory components each having two memory chips are arranged on the right-hand side of the hub chip. Therefore, a total of 18 memory chips have to be driven by the control circuit of the hub chip on both sides of the hub chip.
For driving the memory chips, the hub chip provides four clock signals, of which two clock signals are used for the memory chips on the left-hand side and two clock signals are used for the memory chips on the right-hand side of the hub chip. For this purpose, the hub chip drives two clock buses on the left-hand side and two clock buses on the right-hand side of the hub chip. In accordance with a JEDEC standard, ten memory chips in each case are connected to a first clock bus on the left-hand and right-hand sides of the hub chip and eight memory chips in each case are connected to a second clock bus on the left-hand and right-hand sides of the hub chip. The clock buses thus have the configuration 10/8/10/8.
For selecting a memory chip, the hub chip provides four select signals (Chip Select Signals). Of these, in each case two select signals are used for the memory chips on the left-hand side of the hub chip and in each case two select signals are used for the memory chips on the right-hand side of the hub chip. In accordance with a JEDEC standard, in each case two control buses are available to the hub chip for transmitting the select signals on the left-hand side and likewise in each case two control buses (CTRL buses) are available on the right-hand side of the hub chip. Of the 36 memory chips, nine memory chips in each case are connected to each of the control buses. The control buses thus have the configuration 9/9/9/9.
For addressing individual memory cells of each of the memory chips, the hub chip makes address signals available. For addressing a memory cell of memory chips which are arranged on the left-hand side of the hub chip, the hub chip is connected to a first address bus, a so-called “Command Address Bus” (CA bus) on the left-hand side and to a second address bus (Command Address Bus, CA Bus) on the right-hand side. Of the 36 memory chips, 18 memory chips in each case are connected to each of the two address buses.
On account of the different load distributions on the clock, control, and address buses, performance losses occur particularly in the case of the cards FBD667 and FBD800. The performance losses relate principally to a non-matched timing behavior (“output timing”) of the signals on the different buses. As a result of the different signal propagation times on the different buses, a so-called “early timing” is used on the CA bus particularly in the case of FBD667 and FBD800. In this case, the hub chip emits the different control signals in a delayed manner or in an early manner. However, such a method is very complicated and susceptible to errors since the hub chip has to supervise the control signals on the CA bus and the CTRL bus separately from one another.
In order to obtain a good signal integrity in the FBD667 and FBD800 cards, the memory chips within the semiconductor memory components are provided with an additional input pin, via which a termination resistor (on-die termination resistor) can be switched on. The termination resistor, which is formed as an embedded resistor, is switched on for a write access.
In order to obtain a good signal integrity, it is necessary to provide an on-die termination resistor of an order of magnitude of 50 Ω. However, a termination resistor of 50 Ω has not yet been standardized at the present time. Instead, on-die termination resistors of 75 Ω or 150 Ω are used in accordance with a JEDEC recommendation. However, such resistors prove to be problematic with regard to the signal integrity during writing in the case of a semiconductor memory module of the 2R×4 configuration with “Dual Stacked DRAMs”.
A further disadvantage of an FBDIMM module card in the “Stacked Chip” design is the high costs associated therewith.